#PROGRAM TO DIAGRAM ISA ARCHITECTURE 64 BITS#

Memory model (see the SDM Volume 1, Chapter 3 for details) in real mode In protected mode, applications can choose a flat or segmented The vertical bar means OR, the square brackets mean OPTIONAL, and parentheses are used Not every processor supports every instruction, of course. The following table shows most of the available instructions, using the instruction namesĪs specified in the Intel syntax. See the SDM Volume 1, Chapter 5 for a nice overview of

The machine check registers Instruction Set.

The 5 test registers: TR3, TR4, TR5, TR6 and TR7.

The 8 32-bit debug registers: DR0, DR1, DR2, DR3, DR4, DR5, DR6 and DR7.

The 4 16-bit table registers: GDTR, IDTR, LDTR and TR.

The lower 16 bits of CR0 is called the Machine Status Word (MSW).

The 8 32-bit processor control registers: CR0, CR1, CR2, CR3, CR4, CR5, CR6, CR7.

The registers don’t have names because they are used in a stack-like fashion.Īpplication programmers can remain oblivious of the rest of the registers: There are eight registers used for computing with 80-bit floating point values.

Eight 32-bit floating-point operations in parallel.

Four 64-bit floating-point operations in parallel.

Four 32-bit floating-point operations in parallel.

Two 64-bit floating-point operations in parallel.

Sixteen 8-bit integer operations in parallel.

Eight 16-bit integer operations in parallel.

Four 32-bit integer operations in parallel.

Two 64-bit integer operations in parallel.

You can do operations on 128-bit integers, but you can also take advantage of their ability to do operations in parallel: Use them for floating-point and integer arithmetic. I haven’t used them in 64-bit programming. RIP is the instruction pointer and RFAGS is the flags register.

R0B.R7B have aliases AL, CL, BL, DL, SPL, BPL, SIL, DIL, respectively.R0W.R7W have aliases AX, CX, BX, DX, SP, BP, SI, DI, respectively.R0D.R7D have aliases EAX, ECX, EBX, EDX, ESP, EBP, ESI, EDI, respectively.R0.R7 have aliases RAX, RCX, RBX, RDX, RSP, RBP, RSI, RDI, respectively.You can access the lower order 8-bits of each register using the names R0B.R15B.You can access the lower order 16-bits of each register using the names R0W.R15W.Why? Backward compatibilty! The x86-64 grew out of a 16-bit processor family created in the 1970s. The “D” stands for “doubleword” because strangely, the word “word” on this platform refers to a 16-bit quantity.

You can access the lower order 32-bits of each register using the names R0D.R15D.

#PROGRAM TO DIAGRAM ISA ARCHITECTURE 64 BITS#

These are 64 bits wide and used for integer arithmetic and logic, and to hold both data and pointers to memory. The following diagram is taken directly from Chapter 3 in this volume:Īpplication Programmers generally use only the general purpose registers, floating point registers, XMM, and YMM registers. The basic architecture of the x86-64 is described in Volume 1 of the System Developer’s Manual. The following notes briefly summarize the latter architecture only.

The two massively popular architectures IA-32 and x86-84 are so common, they are described in a single set of manuals. They in no way serve as a substitute for reading Intel’s manuals. These notes summarize a few items of interest about these two ISAs. (Actually Intel 64 was invented by AMD, who called it x86-64). The IA-32 is the instruction set architecture (ISA) of Intel’s most successful line of 32-bit processors, and the Intel 64 ISA is its extension into 64-bit processors.

Program to diagram isa architecture